Intel Builds New Chips with 65 Nanometer Process Technology
"The achievement extends Intel's effort to drive the development of new manufacturing process technology every two years, in accordance with Moore's Law," Intel said in a statement. The transistors in the new 65 nm technology have gates, the switch that turns a transistor on and off, measuring 35 nm, approximately 30 percent smaller than the gate lengths on the previous 90 nm technology, according to Intel.
Pushing the number of transistors it can cram onto silicon, chip giant Intel announced a step forward in its advance to the 65-nanometer manufacturing process, a move toward further miniaturization to boost chip efficiency and performance.
In a sign it is on course to begin manufacturing computer chips with the new process -- and maintain the Moore's Law paradigm of doubling the number of transistors on a chip roughly every two years -- Intel said it had built functional static random access memory (SRAM) chips with more than half a billion transistors using the new process at a facility in Hillsboro, Oregon.
Analysts said the 65-nanometer mark -- even smaller than the recently-introduced 90-nanometer manufacturing technology -- is a significant milestone on the Moore's Law "highway." But the development also highlights the increased pressure on chipmakers to keep up with the Intel's formula for chip advancement, which is now pushing physical limits.
"We're getting into a period where the law of diminishing returns is starting to kick in," said Mercury Research president Dean McCarron, referring to Moore's own predictions that size limitations would become a road block in 2012. "We won't be able to get smaller. The technology will have to change to quantum transistors or something like that."
Intel said transistors in its new 65-nanometer process will have gates measuring only 35 nanometers, which are 30 percent smaller than the length of the on-off switches in the 90-nanometer process. Intel said about 100 of the gates could fit inside the diameter of a human red blood cell.
The company, which has led the way to 90-nanometer manufacturing but has stumbled in doing so, said the new technology also addresses power and heat issues with a "second generation of strained silicon" to cut power leakage and "sleep transistors" that shut off current flow during downtime.
"Intel has been actively working on the power and heat dissipation challenges faced by the semiconductor industry," said Intel senior vice president and general manager of Intel's technology and manufacturing group Sunlin Chou. "We have taken a holistic approach by developing solutions that involve systems, chips, and technologies, and include innovations on our 65nm technology that will go beyond simply extending prior techniques."
IDC program manager Shane Rau said that Intel's announcement is an indicator of the progress toward real volume production using the 65-nanometer processes. Rau said the company is on track to roll 65-nanometer manufacturing into volume next year and is sensitive to the technical issues around the transition.
However, Rau said it is becoming more difficult to keep up with Moore's Law.
"The technical challenges, such as heat dissipation, increase as the industry advances to smaller and smaller process technologies," Rau said.
Gartner research vice president Martin Reynolds agreed, saying that while keeping up with Moore's Law entails investment and complexity, it is a requirement for the industry.
"Moore's Law has always been hard, requiring enormous investments to stay on track, but it is the only way to maintain the replacement cycles on which the semiconductor industry so depends for its revenue," Reynolds said. "The economic issues are the challenge, but Intel continues to beat them. As long as the value can be extracted, the industry will keep up."
Learning from Last Time
Analysts agreed that the difficulty of shifting to smaller transistors and larger complexity showed when Intel transitioned to the 90-nanometer process.
"We saw Intel struggle with power consumption on 90 nanometer," Reynolds said. "The 65-nanometer process will force circuit and system design changes that deal with these issues. Circuit techniques used for mobile products will appear across the range."
McCarron said the "bumpy transition" to the 90-nanometer process demonstrated it is getting harder to maintain Moore's Law. However, McCarron added that is the reason Intel is laying out its roadmap and getting to the 65-nanometer process in stages, such as the announced SRAM chips.
Rival Right There
As Intel has pushed its own manufacturing efficiency and processor performance, rival AMD has remained a steady second, capitalizing on some of Intel's missteps with increased market share and performance advantages.
McCarron said that although AMD might be moving more quietly, the company also is working on the transition to 65-nanometer technology and is partnering with IBM to do so.
"AMD announced for revenue shipments, but it will take them several quarters to catch up with Intel," Reynolds said. "In terms of 90-nanometer maturity, Intel has opened the gap against other manufacturers, in part because of its continued investment through the downturn. But others will benefit from Intel's work, and will catch up."